As a flat panel display apparatus, a Thin Film Transistor Liquid Crystal Display (TFT-LCD) has advantages of small volume, low power consumption, radiation free, relative low manufacture cost and so on, and has been increasingly applied in the field of high performance display.
FIG. 1 shows a configuration of a liquid crystal display including a display panel 100 and driving units. The driving units further comprise a data driving circuit 110, a gate driving circuit 120 and a timing sequence controller 130. The timing sequence controller 130 inputs a clock signal to the data driving circuit 110, and the data driving circuit 110 converts the clock signal and display data into analog signals (D1, D2 . . . Dn) and then inputs the same to data lines of the display panel 100. The gate driving circuit 120 can convert the clock signal inputted from the timing sequence controller 130 into voltage signals (G1, G2 . . . Gm) for controlling pixels in the display panel 100 to be turned on or off, and apply the same to gate lines of the display panel 100 row by row. During the displaying operation of the liquid crystal display, on the basis of the clock signal, the gate lines input control signals to turn on the pixels row by row, and the display panel 100 operates to display according to the data signals on the data lines.
At present, the display panel and the driving units can be connected through interface technology. For example, the interface technology comprises Mini-low Voltage Differential Signaling (Mini-LVDS) interface technology and Point to Point (P2P) interface technology.
With rapid development of display technology, the size of a display panel is larger and larger in order to further improve display effect of a display. However, for the driving units on the display panel, a following problem arises. As illustrated in FIG. 2, taking the Mini-LVDS interface technology as an example, there is a large difference among distances from respective source driver ICs (S-IC for short) on the driving units to the timing sequence controller (TCON) 10, the S-IC close to the TCON 10 will receive the clock signal CLK outputted from the TCON 10 firstly, therefore the clock signal CLK outputted from the TCON 10 arrives at respective S-ICs at different time. For example, as illustrated in FIG. 2, the distance from the S-IC2 to the TCON 10 is smaller than that from the S-IC1 to the TCON 10, and thus the clock signal CLK1 arriving at the S-IC1 has a delay relative to the clock signal CLK2 arriving at the S-IC2 during a T1 phase, as illustrated in FIG. 3, such that a delay error occurs between the data signal D2 outputted from the S-IC2 and the data signal D1 outputted from the S-IC1. Similarly, the clock signal CLKn arriving at the S-ICn has a delay relative to the clock signal CLKn-1 arriving at the S-ICn-1 during a T2 phase, such that a delay error occurs between the data signal Dn outputted from the S-ICn and the data signal Dn-1 outputted from the S-ICn-1. Therefore, the delays between the clock signals CLKs received at the respective S-ICs are different since the distances from respective S-ICs to the TCON 10 are different, such that delay errors will appear among the data signals outputted from the S-ICs and a defective display phenomenon, such as distortion, will occur in the displayed image, and thus display effect of the display will be significantly affected and quality of the display product will be reduced.